Product

AmpForge OTA Compiler

GUI-based OTA sizing tool. Automates transistor-level design of CMOS Operational Transconductance Amplifiers using the gm/ID methodology. Delivers a ready-to-simulate design in minutes.

Key Features

Multi-Arch OTA Support

14 industry-standard OTA topologies — from Differential Amplifier to Class AB Folded Cascode. Both NMOS and PMOS input stage configurations supported across all topologies.

Accurate Transistor Sizing

Uses MOS characteristic data files extracted from foundry SPICE models to estimate transistor sizes and DC current — no hand calculations, no guesswork.

SPICE Netlist Generation

Auto-generates ready-to-simulate SPICE subcircuit netlists with transistor instances, biasing, and PDK compatibility notes included.

Comprehensive Design Space Exploration

Auto Mode autonomously explores the complete transistor sizing space and simultaneously returns three optimised solutions — Low Power, Balanced, and High Slew Rate.

Fine Tuning of Specs

Manual Mode lets you set channel length and overdrive voltage directly for targeted fine-tuning of transistor sizes, DC current, and performance specifications.

Three Optimised Solutions

Every Auto Mode run returns three SPICE netlists simultaneously — Low Power, Balanced, and High Slew Rate — each meeting your specified targets.

Ultra-Fast Design

Complete OTA design ready in minutes — not hours or days. Eliminates the iterative hand-calculation loop entirely.

Report Export

Comprehensive design summary in CSV format — transistor sizes, performance metrics, noise summary, and voltage ranges, all in one output directory.

Easy to Use GUI

Intuitive graphical interface — no scripting or command-line required. All fields are self-explanatory, with real-time console output during the design run.

Specifications

ParameterValue
Version2026.0
PlatformUbuntu 20.04 LTS or later (Linux only)
DistributionZIP archive — self-contained executable
Memory4 GB minimum; 8 GB recommended
Disk space~200 MB for AmpForge + .mdat files
External dependencyNGSPICE (for MOS Characterizer only)
InternetOne-time only (Machine ID + licence file)
Licence typeNode-locked (.lic file, machine-specific)

What AmpForge produces

  • SPICE subcircuit netlist (.sp) — port definitions, transistor instances, biasing, ready to simulate
  • MOS Size Summary CSV — W, L, fingers, ID and VOV per transistor
  • Design Results CSV — DC gain, UGB, Phase Margin, Slew Rate, ICMR, noise achieved vs. target
  • Voltage Ranges CSV — input and output common mode voltage ranges
  • Noise Summary CSV — thermal noise PSD, flicker noise, noise corner frequency, integrated RMS noise

Supported OTA topologies

All 14 topologies support both NMOS and PMOS input stage configurations.

No.TopologyNo.Topology
1Differential Amplifier OTA 8Two Stage Miller RHP Cancel OTA
2Symmetrical OTA 9Two Stage Cascode I/P Miller OTA
3Symmetrical with Cascode Output OTA 10Two Stage Cascode I/P Miller Null Resistor OTA
4Folded Cascode OTA 11Two Stage Cascode I/P Miller RHP Cancel OTA
5Recycling Folded Cascode OTA 12Two Stage Folded Cascode I/P Miller OTA
6Two Stage Miller OTA 13Class AB Two Stage Miller OTA
7Two Stage Miller Null Resistor OTA 14Class AB Folded Cascode Two Stage Miller OTA

The trial licence provides access to 7 topologies: Differential Amplifier, Symmetrical, Folded Cascode, Two Stage Miller, Two Stage Miller Null Resistor, Two Stage Miller RHP Cancel, and Class AB Two Stage Miller. The remaining 7 — Symmetrical with Cascode Output, Recycling Folded Cascode, Two Stage Cascode I/P Miller variants, Two Stage Folded Cascode I/P Miller, and Class AB Folded Cascode Two Stage Miller — require the full licence.

Three solutions per run

In Auto Mode, the Design Synthesizer simultaneously returns three SPICE netlists — each meets your specifications, optimised for a different operating point.

SpecificationLow PowerBalancedHigh Slew Rate
Overdrive Voltage (VOV)LeastModerateHighest
Transition Frequency (fT)LeastModerateHighest
Power consumptionLeastModerateHighest
I/O Common Mode VoltageHighestModerateLeast
Open Loop DC Gain potentialHighestModerateLeast
W/L RatiosHighestModerateLeast
Slew RateLeastModerateHighest

Foundry and PDK support

Pre-built .mdat files are included for three process nodes. For any other PDK, run the MOS Characterizer once to generate the database.

PRE-BUILT · INCLUDED

SCL 180nm

n18, p18, nhv, phv, n5v, p5v models.

n18.mdat · p18.mdat · nhv.mdat · phv.mdat · n5v.mdat · p5v.mdat
PRE-BUILT · INCLUDED

IHP 130nm

sg13_lv_nmos, sg13_lv_pmos, HV variants. Open PDK.

sg13_lv_nmos.mdat · sg13_lv_pmos.mdat
PRE-BUILT · INCLUDED

GF 180nm

nmos_3p3, pmos_3p3, 6V variants. Open PDK.

nmos_3p3.mdat · pmos_3p3.mdat
Any PDK supported. The MOS Characterizer runs with any NGSPICE-compatible foundry model file. TSMC 65nm, GF 180nm 6V, custom nodes — generate the .mdat file once, then use it indefinitely.

Verified results

The following results are from worked Example 1 in the AmpForge User Guide — Two Stage Miller RHP Cancel OTA, SCL 180nm, Auto Mode, High Slew Rate solution.

ParameterTargetAmpForge AchievedSPICE Simulation
Open Loop Gain (dB)5555.2555.38
Unity Gain Bandwidth (MHz)10001000904
Phase Margin (deg)6055.3156.57
Slew Rate (V/µs)350352357
Input Ref. Thermal Noise PSD (nV/√Hz)65.295.72
Input-referred Flicker Noise PSD @ 1Hz (µV/√Hz)—17.517.81
Total OTA plus Biasing Ckt. Current (mA)—1.741.7

Technology: SCL 180nm CMOS · PMOS input stage · CL = 2pF

See your circuit resized.

Trial and full licences available. 48-hour turnaround on the .lic file.

Request Licence